|
|
|
|
| LEADER |
01906nmm a2200289 u 4500 |
| 001 |
EB000353875 |
| 003 |
EBX01000000000000000206927 |
| 005 |
00000000000000.0 |
| 007 |
cr||||||||||||||||||||| |
| 008 |
130626 ||| eng |
| 020 |
|
|
|a 9780387236698
|
| 100 |
1 |
|
|a Shu, Keliu
|
| 245 |
0 |
0 |
|a CMOS PLL Synthesizers: Analysis and Design
|h Elektronische Ressource
|c by Keliu Shu, Edgar Sanchez-Sinencio
|
| 250 |
|
|
|a 1st ed. 2005
|
| 260 |
|
|
|a New York, NY
|b Springer US
|c 2005, 2005
|
| 300 |
|
|
|a XVI, 216 p. 85 illus
|b online resource
|
| 505 |
0 |
|
|a Frequency Synthesizer for Wireless Applications -- PLL Frequency Synthesizer -- ?? Fractional-N PLL Synthesizer -- Enhanced Phase Switching Prescaler -- Loop Filter with Capacitance Multiplier -- Other Building Blocks of PLL -- Prototype Measurement Results -- Conclusions
|
| 653 |
|
|
|a Electrical and Electronic Engineering
|
| 653 |
|
|
|a Electrical engineering
|
| 700 |
1 |
|
|a Sanchez-Sinencio, Edgar
|e [author]
|
| 041 |
0 |
7 |
|a eng
|2 ISO 639-2
|
| 989 |
|
|
|b Springer
|a Springer eBooks 2005-
|
| 490 |
0 |
|
|a The Springer International Series in Engineering and Computer Science
|
| 028 |
5 |
0 |
|a 10.1007/b102174
|
| 856 |
4 |
0 |
|u https://doi.org/10.1007/b102174?nosfx=y
|x Verlag
|3 Volltext
|
| 082 |
0 |
|
|a 621.3
|
| 520 |
|
|
|a CMOS PLL Synthesizers: Analysis and Design presents both fundamentals and state of the art PLL synthesizer design and analysis techniques. A complete overview of both system-level and circuit-level design and analysis are covered. A 16mW, 2.4GHz, sub-2V, S D fractional-N synthesizer prototype is implemented in 0.35mm CMOS. It features a high-speed and robust phase-switching prescaler, and a low-complexity and area-efficient loop capacitance mulitplier, which elegantly tackle speed and integration bottlenecks of PLL synthesizer. This book is useful as a PLL synthesizer manual for both academic researchers and industry design engineers
|